Embedded Software Insight
In part 1 of this series is a complete step-by-step installation and configuration guide for all the tools required to integrate a GCC toolchain within the Eclipse IDE. Including obviously Eclipse and your selected GCC toolchain as well as the MSYS2 UNIX environment for Windows.
This article will look into details the cache configuration for the MicroBlaze that was skipped in part 2. Configuring the cache correctly is critical to the overall performance of a MicroBlaze system and can also take a considerable amount of FPGA resource, especially block RAM. When configuring the cache, the goal is to use the minimum cache size required to meet the application’s performance but no larger.
This article aims at helping developers and designers who must configure a MicroBlaze system. Especially early on in the development process where the final firmware is not available for benchmarking and tweaking. At these early steps it is often necessary to select a good approximation of the final configuration to have a good idea of the resource usage of the MicroBlaze.
This article introduces the various memory hierarchy available when designing a MicroBlaze system using the Xilinx Vivado IP Integrator.
In part 1 of this series is a complete step-by-step installation and configuration guide for all the tools required to integrate a GCC toolchain within the Eclipse IDE. Including obviously Eclipse and your selected GCC toolchain as well as the MSYS2 UNIX environment for Windows.
This article will look into details the cache configuration for the MicroBlaze that was skipped in part 2. Configuring the cache correctly is critical to the overall performance of a MicroBlaze system and can also take a considerable amount of FPGA resource, especially block RAM. When configuring the cache, the goal is to use the minimum cache size required to meet the application’s performance but no larger.
This article aims at helping developers and designers who must configure a MicroBlaze system. Especially early on in the development process where the final firmware is not available for benchmarking and tweaking. At these early steps it is often necessary to select a good approximation of the final configuration to have a good idea of the resource usage of the MicroBlaze.
This article introduces the various memory hierarchy available when designing a MicroBlaze system using the Xilinx Vivado IP Integrator.