Embedded Software Insight
In this article we’ll look at some well-known CPU benchmarks, namely CoreMARK, Dhrystone, Whetstone and Linpack. Following that, we’ll look at the memory bandwidth and latency of the external DDR memory, On-Chip RAM and block RAM (BRAM) in the FPGA. Finally, we’ll round up with numbers on interrupt latency.
Following the last article on core performance this article looks at the MicroBlaze memory bandwidth and access latency. Within the article benchmarks results are presented and discussed for various configuration of the MicroBlaze memory sub system such as local memory, AXI blobk RAM and external SDRAM memory.
Following the success of the MicroBlaze configuration guide this article looks at core performance benchmarks of the Xilinx MicroBlaze using the EEMBC CoreMark benchmark. Like the previous article series, this article looks at various memory hierarchy configurations including local and external DDR memory and their impact on core performance.
This article will look into details the cache configuration for the MicroBlaze that was skipped in part 2. Configuring the cache correctly is critical to the overall performance of a MicroBlaze system and can also take a considerable amount of FPGA resource, especially block RAM. When configuring the cache, the goal is to use the minimum cache size required to meet the application’s performance but no larger.
This article aims at helping developers and designers who must configure a MicroBlaze system. Especially early on in the development process where the final firmware is not available for benchmarking and tweaking. At these early steps it is often necessary to select a good approximation of the final configuration to have a good idea of the resource usage of the MicroBlaze.
This article introduces the various memory hierarchy available when designing a MicroBlaze system using the Xilinx Vivado IP Integrator.
In two previous articles, I have looked at using Micrium’s uC/OS RTOS on the Xilinx Zynq-7000. I only covered kernel and storage. This time, I will be exploring some connectivity options in combination with the Digilent Zybo. Namely, using Micrium’s USB device solution and HTTP server through the Zybo’s Ethernet port. This is also a
This is a continuation of the snickerdoodle adventure, following last week’s successful “hello world” , using Micrium’s µC/OS RTOS. In this series of articles, I’m exploring the capabilities of the snickerdoodle as a development platform for high performance real-time operating systems. This time, I will be running an embedded file system on the snickerdoodle module, enabling
What would make a better first post about embedded software than a hello world project on a brand-new development board. It’s the krtkl snickerdoodle I received with much excitement last week. The SoM is based on the Xilinx Zynq-7000 SoC along with storage and wifi on the SoM. In these next series of articles, I’m
In this article we’ll look at some well-known CPU benchmarks, namely CoreMARK, Dhrystone, Whetstone and Linpack. Following that, we’ll look at the memory bandwidth and latency of the external DDR memory, On-Chip RAM and block RAM (BRAM) in the FPGA. Finally, we’ll round up with numbers on interrupt latency.
Following the last article on core performance this article looks at the MicroBlaze memory bandwidth and access latency. Within the article benchmarks results are presented and discussed for various configuration of the MicroBlaze memory sub system such as local memory, AXI blobk RAM and external SDRAM memory.
Following the success of the MicroBlaze configuration guide this article looks at core performance benchmarks of the Xilinx MicroBlaze using the EEMBC CoreMark benchmark. Like the previous article series, this article looks at various memory hierarchy configurations including local and external DDR memory and their impact on core performance.
This article will look into details the cache configuration for the MicroBlaze that was skipped in part 2. Configuring the cache correctly is critical to the overall performance of a MicroBlaze system and can also take a considerable amount of FPGA resource, especially block RAM. When configuring the cache, the goal is to use the minimum cache size required to meet the application’s performance but no larger.
This article aims at helping developers and designers who must configure a MicroBlaze system. Especially early on in the development process where the final firmware is not available for benchmarking and tweaking. At these early steps it is often necessary to select a good approximation of the final configuration to have a good idea of the resource usage of the MicroBlaze.
This article introduces the various memory hierarchy available when designing a MicroBlaze system using the Xilinx Vivado IP Integrator.
In two previous articles, I have looked at using Micrium’s uC/OS RTOS on the Xilinx Zynq-7000. I only covered kernel and storage. This time, I will be exploring some connectivity options in combination with the Digilent Zybo. Namely, using Micrium’s USB device solution and HTTP server through the Zybo’s Ethernet port. This is also a
This is a continuation of the snickerdoodle adventure, following last week’s successful “hello world” , using Micrium’s µC/OS RTOS. In this series of articles, I’m exploring the capabilities of the snickerdoodle as a development platform for high performance real-time operating systems. This time, I will be running an embedded file system on the snickerdoodle module, enabling
What would make a better first post about embedded software than a hello world project on a brand-new development board. It’s the krtkl snickerdoodle I received with much excitement last week. The SoM is based on the Xilinx Zynq-7000 SoC along with storage and wifi on the SoM. In these next series of articles, I’m